1. Field of the Invention
This invention relates to electrical analog-to-digital converters, and more particularly to a tracking analog-to-digital converter.
2. Description of the Related Art
Analog-to-digital converters (ADCs) are used to translate analog input voltages to digital values which can be used by digital computers. The translation is accomplished by quantizing the analog input voltage and converting the quantization level to a digital code.
Numerous different monolithic ADC architectures are available, such as serial, parallel and subranging. The parallel ADC architecture, commonly referred to as flash converters, provides the fastest currently available approach to quantizing an analog signal. Quantization is effectuated by comparing the analog input voltage to successively higher reference voltage levels. In one type of flash converter a bank of comparators is connected to receive an analog input voltage and predetermined reference voltages. The reference voltage levels are generated using a resistor string which divides the total reference voltage into equally spaced voltage levels of decreasing value to provide different quantization levels within the reference voltage range.
While they are the fastest ADCs at this time, the speed of flash converters is limited by the comparators switching speed, and the resolution is limited by the number of comparators used. When higher speed is required, the process of time interleaving may be used. Time interleaving starts the conversion operation of the second sample before the conversion of the first sample is complete. Although the technique allows for higher operating speed, the resolution is usually lower than for the common flash converters.
The resolution of a flash converter is determined by the number of comparators used. One n-bit resolution digital signal is produced in each conversion cycle. Each additional bit of resolution causes a doubling of the amount of circuitry that is required. The conversion resolution is therefore restricted by the area available for the bank of comparators and string of resistors. Not only do the enormous number of resistors and comparators consume valuable area, it is difficult to produce the low-valued resistors required for flash converters while maintaining the resistor-matching characteristics required for accurate performance. Additional information on parallel ADC architecture can be found in Demler, High-Speed Analog-to-Digital Conversion, Academic Press, San Diego, 1991, at pages 16-18.
Another limitation of flash converters results when a continuously changing analog input voltage is to be converted. Flash converters have an inherent capacitance characteristic which affects their ability to operate on high frequency analog signals. The base-emitter junction of the transistor on the analog input side has an input capacitance with a charging path through the reference ladder. The time required to charge the capacitor causes the reference voltage to lag fast changes in the current which dynamically distorts the voltage division of the reference ladder.
A track-and-hold (T/H) used with a flash converter overcomes this limitation by holding an analog value so that the comparators are always converting a steady value rather than one which is continuously changing. However, by holding the analog voltage constant, the flash converter is not simultaneously quantizing changes in the analog input voltage. The analog input capacitance of comparators and its effect on flash converts is explained in greater detail in Analog Devices, Inc., Analog-Digital Conversion Handbook, P R T Prentic Hall, New Jersey, 1986, pages 423-426.
Serial ADCs offer higher resolution, but, the total conversion time is greatly increased. An example of a serial ADC is the integrating ADC. Integrating ADC's are used in low-speed applications where high accuracy is of primary importance, and are described in Demler, High-Speed Analog-to-Digital Conversion, supra, pages 2-4.
One of the reasons for the high degree of accuracy is that the digital output is directly proportional to the voltage level of the analog input voltage. However, the speed of the integrating ADC is limited by the number of bits of the digital output code. Increasing the resolution by one bit requires double the number of clock cycles. Because of the speed limitations, the integrating ADC is not suitable for converting fast changing analog input voltages.